So what are back end stalls? Superscalar processors can be divided into front end where we fetch and decode instructions, and the back end where these computations are performed.  So during each cycle, the front end generates two of these operations, puts them in the pipeline slots, and moves them through the back end.  But the actual number of retired pipeline slots that contain useful work is rarely equal to this maximum.  And this can be because the back end is not prepareed to accept more operations of a certain kind, so this would be a back end bound execution.  And there are maybe two reasons for this.  An L2 hit bound is when a significant proportion of the pipeline slots remain empty, so when operationstake too long in the back end they introduce bubbles in the pe=ipleine and can cause fewer pipeline slots containing useful work to be retired per cycle than we can support.  This is an opportunity loss and can result in slower execution.  Operations like division and memory operations can cause this, as well as directing too many operaitons to a single execution port.  Or it wcould be L2 miss bound which is th epercentage of cpy cycles spent waiting for l2 load misses to be serviced.  Memory requests missing here have to be serviced by local remote DRAM or MCDRAM which introduces significant latency.