Compiling for Xeon SP
Chris Myers, Steve Lantz
Cornell Center for Advanced Computing
Revisions: 4/2024, 1/2022, 2/2021 (original)
Well-chosen compiler options can be valuable in producing high-performing code for Intel Xeon Scalable Processors, such as the Intel Skylake processors integrated into Stampede3, and the Cascade Lake processors at the heart of Frontera at TACC. Major compilers, including the Intel compilers and GCC, provide a broad range of architecture-specific options for this purpose. This topic covers the most important options and details to know when compiling your C, C++, or Fortran code for Intel Xeon SP architectures.
Objectives
After you complete this topic, you should be able to:
- Identify important compiler options for codes that will run on Xeon SP processors
- Explain how to specify a target architecture to the Intel and GCC compilers
- Describe differences in the AVX-512 instruction set between successive generations of Xeon SP processors
- Explain why code compiled for AVX2, instead of AVX-512, might run faster on Xeon SP processors
- Compile a simple code for a Skylake (SKX) or Cascade Lake (CLX) processor and run it successfully
- Explain how to choose OMP_NUM_THREADS appropriately for different processor types
Prerequisites
- Familiarity with High Performance Computing (HPC) concepts. Those who are less conversant with HPC terms and techniques should be prepared to inspect the glossary terms rather frequently. It may also be helpful to review Cornell Virtual Workshop content on Parallel Programming Concepts and High-Performance Computing and either MPI or OpenMP.
- Programming experience in C or Fortran. Introductions to C and Fortran are available, though the reader will need to look elsewhere for a full tutorial on these languages.
- Readers who need an introduction to either Stampede3 or Frontera will find it helpful to first review one of more of the following items: the Stampede3 User Guide, the Frontera User Guide, and the Getting Started on Frontera CVW material.