Back end stalls refer to the phenomenon of CPU pipeline slots being empty while waiting for data to move, which can arise due to various causes.

Key points:

• L2 hit bound refers to cycles that are spent retrieving data from L2.
• L2 miss bound refers to cycles that are spent waiting for data outside of L2 to be brought into L2.
• The Application Performance Snapshot reports the percentage of empty slots associated with these different causes, as well as the total number of cache misses.